Q-point constant multipliers for FFT processors

Multiplication of the data with several constants forms the basis for many Digital Signal Processing (DSP) and multimedia applications like in Digital Filtering, in Image Processing DCT and DFT. Most portable devices or handheld devices such as MP3 players, mobile phones, DSLR etc involves large number of multiplications with the several constants. FFT processors also involve large number of complex multiplication operations. As the multiplication operation takes more time they result in an increased delay in the FFT processors with larger area and energy consumption. This paper presents an hardware efficient implementation of the constant multiplier which make use of Q-Format representation to improve the speed of the multipliers as speed plays a crucial role in FFT processors along with Common Subexpression Elimination (CSE) technique and Canonical Signed Digit (CSD) representation to reduce the number of adders hence reduce hardware usage. The design is coded for 8bits, 10 bits and 16 bits fractional fixed point multiplications using Verilog and has been implemented in Altera, device Cyclone IIEP2C35F672C6.