On-chip memory for image processing applications based on FPGA

In Image processing applications the utilization of on-chip Static Random Access memory (SRAM) in Field Programmable Gate Array (FPGA) is extremely important. True dual port (TDP) SRAM and Single port SRAM are typically available SRAM's for image processing applications, but in case of data access policy the memory need to redesign. Hence On-Chip memory architecture capable of scanning the data in different ways without redesign. In the proposed sub bank Dual Port Memory Architecture SP SRAM has been modified to functions as TDP SRAM with high throughput less power consumption. It also provides High level of abstraction for image processing algorithms with the help of two port memory control unit, clock and address generators, the proposed sub bank read and write operations are takes place without compromising the speed.