Multi-rate polar codes for solid state drives

As solid state drives (SSDs) are gradually replacing hard disk drives, error correction is critical to SSDs since NAND flash has deteriorating reliability over their life span. Existing error correction codes suffer from limited error correction capability or error floor issues. Polar codes are promising for SSDs since they are theoretically proven optimal codes and have good error floor behavior. In this paper, we first design multi-rate polar codes for SSDs, and then implement encoder and decoder that simultaneously support multiple rates in FPGA. Multi-rate polar codes provide a good tradeoff between reliability and efficiency. Finally, we use an FPGA emulation platform to evaluate the error performance of our polar codes, and examine their error floor behavior.