XSG for hardware implementation of a robust watermarking system

In this paper, we present a novel hardware implementation of a watermarking system applied on the digital image. The proposed hardware system is based on the DWT (Haar discrete wavelet transform) on the first level of the decomposition. The watermark is hidden in the LH
₀
(mean frequency sub-band) in goal to get a maximum of the compromise between the visibility and the robustness factors against several attacks. The ML507 Evaluation Platform, which is based on the Virtex-5 FPGA, is choosing for testing the hardware cosimulation of the proposed architecture. The proposed hardware design give good results in term of the rapidity execution and in term of the robustness against various attacks such as: impulsionnel noise, filtering attack, compression and the geometric transform.