Radiation-induced SET on Flash-based FPGAs: Analysis and Filtering Methods

Reliability of Integrated Circuits (ICs) it is nowadays a major concern for deep sub-micron technology. The progressive decreasing of device feature sizes provokes an increasing sensitiveness to radiation-induced particle strikes within the device silicon structure generating a larger number of Single Event Transients (SETs). In the present paper, we propose a new analysis to characterize the SET phenomena within Flash-based FPGAs. Besides, we developed a new mitigation strategy based on the modification of the place and routed design to improve the filtering capability selectively adding electrical resistive capacitive loads without introducing performance degradation and introducing a limited overhead in terms of routing segments. Experimental results performed on a various set of benchmark circuits shows a mitigation of SET improved of 3 orders of magnitude with respect to traditional logical filtering solutions with a minimal performance degradation of about 9%.