A hardware accelerated proportional text layout and placement engine

Web browsers and e-book are some of the most dominant applications on mobile devices today; they spend a significant amount of time handling the layout design of text. Many efforts have been made in software to improve the performance of text layout and display but none have consider dedicated parallel processing hardware schemes for System-on-Chip (SoC) devices. This paper introduces a new hardware-software hybrid system to perform the layout and placement of proportional text by using a small hardware module which can easily be added to the SoCs of today's mobile devices. An improvement of 27× in text layout and 23× on average in text placement was measured against a software only model on the same FPGA development platform.