Formation of through-silicon-vias by Tin filling processes using pressure infiltration and electrodeposition/reflow

Three dimensional electronic packages have been extensively investigated to meet the ever increasing needs for size reduction and performance improvement of electronic devices. To overcome the disadvantages of conventional wire bonding in 3D packages, through-silicon-vias (TSVs) filled with Cu has been proposed as a new chip-to-chip vertical interconnection. In addition, TSVs can be also used as thermal vias for effective heat dissipation of a device. Cu TSVs can provide shorter interconnection than wire bonding, resulting in high-frequency-characteristics improvement and size reduction of chip stack packages. However, via-filling process with electroplating of Cu requires a long process time and a complicated control of process variables, becoming a bottleneck for TSV formation. In this study, formation of TSVs using pressure infiltration of molten Sn into via-holes was investigated as a new via-filling method to replace the Cu filling process. Sn via-filling behavior has been investigated with variations of infiltration pressure, infiltration time, and via-hole dimensions. In this work, we also studied TSV formation by Sn via-filling using Sn electrodeposition into via-holes and its reflow.