A unique failure mechanism induced by chip to board interaction on fan-out wafer level package

Despite many fatigue mechanisms published for Fan-out Wafer Level Package (FOWLP), most merely focused on stand-alone package reliability or solder joint capability. Only a few explored the failures of Chip to Board Interaction (CBI) due to the difficulty for perceiving the induced CBI failures. In this paper, a unique failure mechanism was first observed by an innovative test methodology in interconnects of FOWLP induced by CBI under thermal stress gradient. Circular cracks were detected on passivation and redistribution layer (RDL) owing to mismatched thermal expansion among modules. CBI were studied and improved by appropriate passivation properties, fine-tuned process window, optimized RDL patterns and suitable solder ball material. A novel simulation model was established and an in-house design guideline was generated for reliability robustness.