Reducing Qrr in high-voltage SuperJunction MOSFETs by using the cascode configuration

In this paper, the reverse conduction behavior of a Cascode Configuration (CC), combining a High-Voltage (HV) SuperJunction MOSFET (SJ-FET) and a Low-Voltage silicon MOSFET (LV-FET) is deeply scrutinized by means of an analytical model and experimental data. The reverse recovery charge (Qrr) of SJ-FETs in CC with LV-FETs (SJ-CCs) is investigated in this work. As a result of the study, it has been found that the proposed SJ-CC avoids or mitigates the conduction of the SJ-FET body diode during reverse conduction. As a consequence, the Qrr achieved by the CC is several times lower than in the case of the standalone configuration. Moreover, the Qrr reduction achieved results in record-low Qrr for 600 V-range silicon transistors at a fixed on-resistance (RDSON).