Dual-threshold single-ended Schmitt-Trigger based SRAM cell

Data retention and power consumption during the hold mode of operation of a SRAM cell is of high importance. Hence, there is a need for a cell design that improves Static Noise Margin (SNM) and consumes low static power. This paper presents a Schmitt-Trigger (ST) based Single-Ended 11T SRAM cell that uses dual-threshold CMOS technology which exhibits high read and hold SNM and consumes low power during the hold operation. The cell is implemented in 45 nm CMOS technology using Cadence Virtuoso at supply voltage of 0.45 V. The simulation results show 89.11% decrease in the average static power dissipation of the proposed cell during the hold and read modes of operation and 38.93% decrease during write operation, when compared to that of the existing ST 11T SRAM cell for which the floating node is replaced with ground for simulation purposes.