Performance analysis of decimal matrix code and modified decimal matrix code

This paper presents a method of increasing reliability of memory, so as not to make the data erroneous, and to make the data free from multiple cell upsets (MCUs). There are many methods to increase the reliability of memory, but in this paper a modification to decimal matrix code is proposed with reduced redundant bits. The error correction codes which are used to protect memories and to increase the reliability of memory are more complex, because of the shrinking of CMOS technology. The proposed technique increases error detection capability due to the use of decimal algorithm. In the existing decimal matrix code there are more number of redundant bits, which are required for the detection and correction of the data in the memory. In this paper same algorithm as that of decimal matrix code is used but, the number of redundant bits are reduced and it also has less area and power.