Time-parallel multi-delay logic simulation

Multi-delay logic simulation may perform many logic simulations for each gate in the circuit during the simulation of a single input vector. Conventional event driven simulation will perform each of these gate-simulations as a separate operation, producing a single bit of information for each operation. The PC-Set method eliminates the scheduling code of event-driven simulation at the expense of performing unnecessarily gate simulations. This permits much faster simulations except when the activity rate is extremely low. Time-parallel simulation can perform the required simulations for a single gate simultaneously. Up to 64 gate simulations can be performed using a single set of low-level operations. Previous work on time-parallel simulation was done many years ago, and due to resource limitations, it was limited to unit-delay simulations. Modern computers are not so limited, and are able to perform time-parallel multi-delay simulation with no problems. Time-parallel simulation significantly out-performs both conventional event-driven simulation and the PC-set method. Furthermore, recent work in oblivious simulation (time-parallel simulation is an oblivious technique) suggests that oblivious simulation can perform well even with extremely low activity rates, thus permitting time-parallel simulation to outperform conventional event-driven simulation under most conditions.