High sigma statistical hold time analysis in FinFET sequential circuits

Accurate hold time analysis of sequential cells is crucial to high performance enterprise server microprocessor circuit design. Due to tight timing margins, process variation, and increased instance counts of latches and flops in a microprocessor, fast and accurate hold time analysis with process variation consideration is needed. In this article, we present a novel, high-sigma, SPICE-based analysis methodology that accurately characterizes hold time of a sequential cell with margin for multi-million instances on a chip. The methodology reduces the sample count significantly by using a distribution transform from Gaussian to Uniform, and derives the hold time within 0.5ps accuracy on a target functional yield. The methodology has been implemented in an automated flow and used in FinFET production library analysis. Analysis results demonstrate that corner-based hold time analysis can be up to 20ps more pessimistic than statistical analysis, resulting in over design. In some cases, corner-based hold time can be 5ps more optimistic than statistical results, indicates potential violation under process variation. It is important to perform statistical hold time margin analysis for sequential circuits in order to ensure the success of the high performance requirements of enterprise class of server microprocessors.