Design of low power and high speed phase detector

High-speed phase frequency detector (PFD) is one of the key module for high-frequency phase locked loop (PLL) systems. The performance of PLL depends on the operation of PFD. This paper presents a new PFD design in 0.18μm CMOS technology using 3T XOR and 3T NAND gates. Supply voltage has been varied from 1.8V to 2.4V in the proposed design. The new PFD consumes power within a range from 505.78μW to 1310.80μW when operating at 500 MHz clock frequency. Results have been compared with conventional MOS current mode logic (MCML) design and the proposed design shows less power consumption. The proposed PFD is a useful circuit for low power and high-speed PLL systems.