Fault simulation and analysis of VLSI circuit using n-detect test sets

Identifying the faults in the electronic circuits is a hard process. Hence, detecting a flaw more than one time has high degree of fault coverage. Previous works shows that n-detect test sets are of increased quality for a number of common defects. Method for multiple detect test generation usually produce fully specified test vectors. These fully specified bits increase the complexity of the test process. In order to avoid this, this paper goes in for a new technique of increasing the unspecified bits so as to minimize the compactness of the vectors that is used (usage of n-detect relaxed algorithm). S27 Benchmark circuit is used to analyze the process, where single Stuck-at-faults are introduced arbitrarily and the test process is carried out using 4- bit sequence pattern of 16 combinations. These patterns are generated randomly by using LFSR. The patterns that are generated, flow through the entire circuit, and compare it with the faults that are present in the components, either at the input or output. During the comparison if the component response and the pattern response are same, then it is considered as a fault free component. If the response differs, they are considered as fault and are recorded. In this manner many patterns detect the same faults or different faults. The patterns that detect the same faults are grouped together and are reduced into single pattern with unspecified bits which is denoted by ‘x’. These unspecified bits are obtained by comparing these patterns, in bit wise manner. We use saboteurs and mutant techniques for test pattern reduction and comparing the output with relaxed n-detect test set. This process can be clearly demonstrated by using MODEL SIM 6.3f and Xilinx ISE 9.2isimulator