Floating point unit using error correction scheme and modified anticipator

This paper presents architectures for user defined floating point add subtract unit with modified leading Zero Anticipator (LZA). In floating point addition unit, adder and normalization unit decides critical path delay. Predicting the shift amount before the adder output helps in reducing the delay introduced by the normalization. Most of the available algorithms are inexact in nature. They predict the shift amount with a possible error of 1 bit. Thus, these LZA algorithms need an error detection circuit. Proposed error detection logic is implemented in parallel with adder and taking inputs from LZA. With the proposed method we can achieve the reduction in the delay by 18.98% when compared with the conventional floating point unit. Also the proposed error detection and correction method reduces the error occurrence possibility in the result obtained.