Design of low power Schmitt trigger logic gates using VTCMOS

This paper presents Subthreshold Design of Schmitt trigger logic gates for low power operation by using Variable Threshold CMOS Technique (VTCMOS).The proposed design of Schmitt trigger are form on buffer design using dynamic threshold MOS (DTMOS) for better low power operation. By improving the Schmitt trigger to AND/OR/XOR Gates, with minimum switching power consumption as well as area reduction in comparison with CMOS Schmitt triggers, at the cost of a slight increase in delay. The performance characteristics of Schmitt trigger gates have been analyzed in term of power dissipation and delay using predictive Technology models at 180nm technology node for both CMOS and VTCMOS Schmitt trigger.