A hardware FPGA implementation of a 2D median filter using a novel rank adjustment technique

This paper presents the design and implementation on a field programmable gate array (FPGA) of a 2-D median filter, which is capable of obtaining a median value every clock cycle. The device is designed to operate in real-time with rates of over 80 megasamples per second on n-bit sample sequences. Also, the operation speed remains constant regardless of the size of the selected mask N.