Key Issues and Solutions for Characterizing Hot Carrier Aging of Nanometer Scale nMOSFETs

Silicon bandgap limits the reduction of operation voltage when downscaling device sizes. This increases the electrical field within-a-device and hot carrier aging (HCA) is becoming an important reliability issue again for some CMOS technologies. For nanodevices, there are a number of challenges for characterizing their HCA: the random charge-discharge of traps in gate dielectric causes “within-a-device-fluctuation (WDF),” making the parameter shift uncertain after a given HCA. This can introduce errors when extracting HCA time exponents and it will be shown that the lower envelope of the WDF must be used. Nanodevices also have substantial device-to-device variation (DDV) and multiple tests are needed for evaluating their standard deviation (σ) and mean value (μm). Repeating the time-consuming HCA tests is costly and a voltage-step-stress method is applied to reduce the number of tests by 80%. For a given number of devices under tests (DUTs), there is a little information on the accuracy of the extracted σ and μm. We will develop a method to provide this information, based on the defect-centric model. For 40 DUTs with an average of ten traps per device, the extracted μm and σ has an accuracy of ±14% and ±24%, respectively, with a 95% confidence.