32 bit power efficient carry select adder using 4T XNOR gate

Adders are the basic elements used in complex data processing for efficient VLSI design. The CSLA adder circuit is used for the design of high speed processors. There is scope for decreasing the power and area of the design while preserving the speed of the circuit in CMOS technology. The CSLA adder architecture is such that it is of less power dissipation, area efficient and high speed. In this paper 4transistor XNOR gate is used to design the hybrid CMOS Full Adder circuit. The CSLA circuit is designed using this hybrid CMOS Full Adder circuit for 8-, 16-, 32-bit and parameters like area, power and delay are compared with that of the regular CSLA. Here the excess logic operations in the regular CSLA are eradicated and a new logic operation for the modified CSLA is formulated before the final sum calculation is proposed. The power consumed by the modified XNOR and Full adder is 0.5595mW and 1.273mW respectively. In this paper design work is compared with the regular CSLA adder with parameters like area, power and delay through 180nm CMOS process technology and implemented in Cadence Virtuoso tool. The results show that modified CSLA is more efficient than the conventional CSLA in terms of area, power and delay.