Development of mathematical models for standard cells timing analysis at the 28 nm technology and below

The impact of negative short-channel effects in transistors is increasing with the shrinking of geometrical sizes especially at the 28 nm technology and below. The usage of FinFET technology instead of standard planar CMOS for 22 nm node and below provides a solution of problems with short-channel effects. Paper is devoted to research and development of mathematical models for timing analysis of standard cells at the nanometer VLSI technology. Proposed graph theoretical model for logic elements of CMOS technology with 3D gate of the transistor, which suitable for standard cell layout formation. The introduced model is based on using SP-NM-graph of series-parallel structures. This model allows the analysis of the circuit timing on the basis of Elmore delay model for the specific transistors and their parallel and serial connections. It is proposed to replace each transistor of cells to its equivalent Pi-model. In this paper the formulas for calculating the conductance and capacitance of transistors are derived. In this approach, the gate delay is represented as a product of its equivalent resistance and capacitance of the output node. We considered only a common use case for Gaussian elimination for translation of RC-model to equivalent Pi-model with point of Elmore delay view.