TCAD simulation of TFET structures integrated in basic CMOS technology

Characteristics of the tunnel field-effect transistor (TFET) formed on the basic layers of CMOS process are investigated by Synopsys TCAD tools. The structure of the planar TFET integrated in CMOS technology is considered and the dependence of on-state TFET current from the source implantation dose is obtained. A CMOS-compatible non-planar TFET configuration with shallow-trench areas is analyzed as a variant of increasing the TFET tunneling area and hence the on-state TFET current. The influence of the source doping distribution and the shape of the drain region on the working current have been analyzed for the non-planar TFET with the annular gate. The selected variant of design enables to increase the on-state current density be three times compared to the initial CMOS-based TFET structure.