Usage area and speed performance analysis of booth multiplier on its FPGA implementation

The aim of this paper is to design multiplier circuits for artificial neural network applications. The efficient use of area and speed performance has become a challenging task VLSI design field. In this works, radix-4 booth multiplier and radix-2 booth multiplier algorithms are analyzed based on its area used and speed performance. The less area used means the multiplier is more efficient in usage area, the smaller the delay means that the speed of the multiplier is higher. The design is accomplished using Xilinx Spartan-6 LX16 Field Programmable Gate Array (FPGA).