Performance optimization and power efficiency in 3D IC with buffer insertion scheme

We present a new scheme of buffer implementation in through-silicon via (TSV) based 3D circuits at early layout design stage for total delay minimization. For optimal buffer insertion at floorplanning level, it is important to incorporate more accurate and realistic estimation of interconnect delay and power. Early prediction of delay and power leads to better design decisions, overall timing closure and design convergence. The proposed buffer insertion scheme is integrated within the nets-to-TSVs assignment process, therefore considers the actual TSV position during buffer planning around TSVs. This method significantly minimizes signal degradation across TSVs while also avoiding excessive usage of buffers. We demonstrate that the choice of nominal wire length, which is a fixed interval between adjacent buffers, plays a critical role in the delay and power prediction of buffered interconnects. The nominal wirelength in our approach is represented by a multiplicity of the TSV equivalent wire length, which effectively models the TSV RC delay contribution to delay of a net. We compare the efficiency of our proposed scheme with existing buffer insertion techniques in 3D circuits. The power efficiency achieved by 3D circuit incorporating the proposed buffer insertion scheme is shown to be 38% higher than in 2D implementation of the same circuit.