A novel efficient adiabatic logic design for ultra low power

With the continuously growing quest for miniaturization of circuit technology, one of the prime focuses of the research has shifted in the direction of ultra low power circuit designs. Over the years, adiabatic circuit designs have been studied and found to be effective in achieving low power in VLSI circuits. This paper briefs some of the adiabatic logic families such as ECRL, 2N-2N2P and PFAL. And presents a new adiabatic logic circuit based on PFAL logic family. This paper aims at comparing the effectiveness of proposed adiabatic logic circuit, in terms of power dissipation, over other adiabatic logic families by simulating different logic gates using these logic families. All the simulations are done using HSPICE Simulator at 65nm technology at different frequency range. Comparative results are presented by different bar graphs plotted at different frequencies, which shows least power dissipation for the proposed logic circuit.