Low power methodology for wishbone compatible IP cores based SoC design

The IP (Intellectual Property) cores from Opencores are portable building blocks described at RTL level; most available components are wishbone bus compatible. These IP cores have been used in numerous SoC architectures. The benefits of using these IPs are flexibility, reusability and also reduction of the whole design cost owing to the accessibility of these IP cores for free. However these IPs are not designed with low power saving features, which is an important issue in SoC design. In this paper, we propose a low power strategy for wishbone compatible IPs based SoC design using an IP level clock gating. The aim is to reduce power in the whole SoC based on these IPs, designed with low power saving features. Primary results show that the proposed scheme at IP level achieves dynamic power reduction, ranging from 31 % to 66.4%.