New scalable digit-serial inverter over GF(2m) for embedded applications

This paper presents new scalable digit-serial inverter architecture with low circuit complexity to perform inversion operation in GF(2^m) based on a previously modified extended Euclidean algorithm. The architecture size can be modulated to be suitable for fixed size crypto processors used in embedded applications. Implementation results of the proposed design and previously reported efficient designs show that the proposed scalable structure achieves a significant reduction in area ranging from 83.0% to 88.3% and also achieves a significant saving in energy ranging from 75.0% to 85.0% over them, but it has lower throughput compared to them.