Investigation of Floating Gate Implantation Effect on 1Xnm NAND FLASH

Continuous scaling down NAND FLASH toward below 2Xnm node generation will result in serious Floating Gate (FG) poly depletion due to dopant loss and significantly degrade the cell reliability performance. FG implantation (IMP) before inter-poly-dielectric (IPD) deposition was proposed in this study, but it suffered FG damage and resulted in control gate (CG) void issue. We have successfully minimized the FG damage and hence the void-free CG can be obtained by reducing the implanted beam current, increasing the implanted rotation times, and adding post rapid thermal annealing (RTA) process. Finally, the optimized FG IMP processes were validated at 1Xnm NAND FLASH device and displayed significantly improvement on FG depletion and cell reliability.