Accelerating SVD computation on FPGAs for DSP systems

This paper presents a fast and generic hardware architecture for channel matrix singular value decomposition (SVD) in massive multiple-input multiple-output (MIMO) system. A fixed-pointed pipelined hardware architecture which implemented Hestenes-Jacobi method was developed to reduce the computing time in order to adapt real time processing requirements. Our proposed design was implemented on a Xilinx Kinect-7 series FPGA, which achieved an 8.5x to 15.3x improvement in speed when compared to software implementation by using MATALB and a 2.1x to 6.3x speed-up when compared to using general-purpose GPU programming scheme in processing 8×8 to 128×128 matrices.