Analysis of power dissipation in design of capacitorless embedded DRAM

This paper presents a new DRAM architecture for scaled DRAMs. Recently the semiconductor industry tends to design a smaller volume device and system with lower power consumption, lower leakage current, and high speed performance. Semiconductor memory arrays capable of storing large quantities of digital information are essential to all digital system. This paper analyse effect on power dissipation of 3T-1D DRAM by variation in voltage. Day by day DRAM is more used as compare to SRAM because of cell area decreases as number of transistor decreases from SRAM to DRAM design.