Simulation study of logic circuits using optimized graphene nanoribbon FETs

Si CMOS has been the driving potential behind tremendous achievements obtained in the field of electronics, computing and telecommunications. However there is a need to explore alternative device technologies that could somehow either complement the existing CMOS technology or replace it, as it advances it's saturation point. Graphene nanoribbon Field Effect Transistors could serve as an alternative as it utilizes the extraordinary properties associated with Graphene. This paper investigates the performance of basic logic circuits such as 2:1 Multiplexer, Half Adder & FO4 Test Chain designed with the help of optimized GNRFETs. The observations demonstrate that optimized GNRFET based logic circuits outperforms its CMOS counterpart, especially in terms of PDP. The effect of scaling supply voltage on performance parameters was also studied.