An 8-bit segmented current steering DAC for low power communication applications

Digital Signal Processing has become popular these days because of development of data converters with high resolution and high speed. Analog to Digital Converter (ADC) and Digital to Analog Converter (DAC) are integral part of Digital Communication Systems for Data Conversion. The objective of the work is to design an 8-bit segmented current steering Digital to Analog converter (DAC) operating at low power. Segmented architecture uses combination of Generic and Binary Weighted Current Steering DAC architectures. Here we use 4-4 segmentation, i.e. 50% segmentation. Current Steering DAC was chosen, considering High Speed and High Power efficiency, over other DAC architectures. The designed Current Steering DAC operates at 1.2 V in 130 nm CMOS Technology, with power consumption of 14.725 mW and effective chip area of 0.177 m³.