Optimisation of 9T SRAM bit cell geometry for high speed memories

In this paper, 9T bit cell is designed and simulated to verify the design. The design and simulation study results are presented here. 9T SRAM bit cell is designed with 65nm CMOS technology, obtaining optimum transistor geometries for the bit cell. Leakage current for the designed bit cell is estimated for variations in transistor geometries, VDD and temperature.