Automated characterization of reverse recovery parameters in high speed LDMOS devices

Measuring and quantifying reverse recovery parameters in high-speed LDMOS devices is an important task in their characterization. Multiple topologies have been proposed to quantify the revere recovery time, reverse recovery charge, and reverse peak current. Although such topologies have achieved different levels of performance, still they offer opportunities for improving in the handling of high-speed devices. This paper proposes modifications to the JEDEC standard test setup that enable a 5X speedup when compared to the original circuit. A virtual user interface (VI) developed for the modified circuit is also presented. The combined operation of the VI and test setup are evaluated on commercial off-the-shelf and wafer-level devices to demonstrate their functionality.