Toward better layout design in ASTRAN CAD tool by using an efficient transistor folding

Traditional synthesis flows dedicated to design ASICs usually adopt the standard cell approach to generate VLSI circuits. Consequently, chip-level layout is not fully optimized due to the restricted number of cells present in the library. To reduce this problem, ASTRAN, an academic open source automatic synthesis tool, was developed. This tool generates layouts with generic cell structures and obtains results with similar density compared to handcrafted cells. A key step on the ASTRAN flow is the transistor folding, which consists in breaking larger transistors that exceed the maximum height limit for the layout of the cells. However, this step is executed in ASTRAN only into single transistors. This work optimizes this strategy introducing a new approach to the folding technique, which identifies all transistors stacks and applies folding for each of these arrangements. The results obtained through this approach show reductions in geometrical and electrical aspects in the layout.