Low-power bootstrapped sample and hold circuit for analog-to-digital converters

In this paper, a modified low-power bootstrapped sample and hold (S/H) circuit is proposed. The effect of the proposed modified low-power bootstrapped sample and hold (S/H) circuit appears in the medium and high-frequency applications in which it reduces the power consumption without affecting the signal-to-noise and distortion ratio (SNDR). The proposed modified low-power bootstrapped sample and hold (S/H) circuit is based on eliminating the multiplier circuit which is responsible for keeping the gate-source voltage of the sampling transistor constant and replaced it with a PMOS transistor which performed the same job. In addition to that, it is based on using the transmission gate as the sampling transistors which avoid the degradation of the signal-to-noise and distortion ratio (SNDR). All the introduced bootstrapped sample and hold (S/H) circuits were simulated using 90nm CMOS technology on LT Spice IV. As a result, the proposed modified low-power bootstrapped sample and hold (S/H) circuit saves 70% to 92% of the power consumption compared with previous work reported in the literature with signal-to-noise and distortion ratio (SNDR) of 57 dB for 7 MHz input frequency signal.