Optimization of SRAM and application

This paper presents an optimized SRAM that is repairable and consumes less power consumption. To increase the number of good SRAMs per wafer, redundancy logic and e-fuse box are added to SRAM, thereby building SR SRAM. In order to reduce power consumption, power on and off states are added into SR SRAM, consequently constructing LPSR SRAM. Also the testing method of the SoC which has been successfully tapped out in 90nm CMOS process is discussed. The test results indicate that 20.45% of power saving is obtained to the LPSR SRAM64K×32 and the percent of the good LPSR SRAM64K×32s per wafer is increased by 16.32%.