System level modeling of supply noise induced jitter for high speed clock forwarding interfaces

Power supply noise induced jitter is one of the dominant timing error components in high-speed I/O interfaces. Designing a high-performance, reliable PHY (Physical Design) requires accurate prediction of supply noise jitter and its impact on the overall system, not solely the component level. Clock forwarding interfaces help reduce the impact of supply noise jitter at the system level as the most common types of jitter can be tracked. Therefore, high-performance, yet cost effective interface designs require accurate modeling of both jitter and system-level margin loss. This paper covers the key fundamentals of supply noise jitter modeling and jitter tracking. Crucial models and formulae are derived and verified, and important design optimization steps are explained in a holistic view. For example, DDR4 PHY design optimization is considered for demonstration.