The exploration and characterization of insulated Au-Flash PdCu wire bonding applications

The bonding feasibility of Insulated Au-Flash PdCu (X-PdFlash) has proven to be successful in many of the previous studies shown in various papers. This has given the confidence of this collaborative project to explore into other areas of bonding applications with potential challenges on insulated Au-Flash PdCu wire. One critical potential area of study would be in Ultra-Low-Loop(ULL) application down to 2mils loop height. Since at such low loop height, the critical loop bendings would occur at the bonded ball neck region which is subjected to the high energy effects during EFO sparking, this could result in regional peeling-off of the insulation coating on the wire due to the partial breaking down or weakening of the insulation layer and bending stresses incurred at the ball neck region. Thicker insulation coating may complicate ULL applications further as this would mean sharp bending through thicker coating material with little ductility. Uneven wire surface contact with the capillary internal walls also sets in and thus resulted in the regional insulation material peeling as illustrated in the paper. Various loop profiles were also studied to assess for any improvements to the ULL application. Another challenging application would be in conventional stitch bond on bump process. The bumped ball smoothing action could result in excessive accumulation of insulation material at the capillary tip, thus causing fast-clogging of the capillary which means an increase in the production costs due to a shorter capillary life-span. This is even so when the insulation coating layer gets thicker. At the same time, insulation material residue that was left on the bumped ball surface prior to the 2^nd bond adhesion could result in poor bondability and workability of the stitch bond on bump process. Besides, the flexibility of insulated wire which enables the criss-crossing wire layout was fully adopted into a universal substrate concept for ball grid array (BGA) packaging. The idea is to use one standard substrate design and caters to multiple devices / products. In this case, insulated wire bonds are assigned freely as device specific trace routings in substrates are not required. This idea able to reduce substrate design cycles and at the same time lowers the substrate unit cost. The development performed by NXP with the use of insulated wire has demonstrated good wire bond process feasibility without any major process issue. Thickness of the insulation layer becomes more critical as we explore into wider areas of bonding applications. In finer pitches where every um counts and tolerances of capillary becomes much narrower, any variations to either the insulation coating layer itself or the bonding processes used could affect the overall stability and bondability of insulation wire [1]. Series of assessments were performed to assess the performance of various insulation thicknesses in terms of wire bondability, electrical insulation and wire bond quality. Eventually, a new insulation thickness window in terms of break down voltage (BDV) was established that able to fulfill all the requirements. In summary, the development on various wire bond technologies with insulated wire has widened the application of insulated wire. Detailed wire bond process optimization and characterization successfully improve the feasibility of new insulated wire bond technology. This indicates another great leap in the insulated wire bond application.