Design and optimization of molding process for MEMS WLSCP

The objective of this paper is to investigate the molding process in MEMS wafer level packaging solution. In this approach we adopted conventional molding process to complete the MEMS capacitive sensor packaging in order to achieve cost-effective full wafer-level packaging solution. It is important to secure void free molding because any voids generated nearby the eutectic bonding area will impair the reliability of the package. Molding process was investigated in terms of cavity formation methods, i.e., the combination of DRIE (Deep Reactive Ion Etching) and partial dicing, or full Si DRIE method. The Si wafer could be fully or partially etched in wafer thickness direction to expose Si pillars. By partial etched method, the backside of the Si Pillars is connected as a whole. Dicing lines works as a portal for mold feeding. Although this method is a bit complicated in the process flow, the large blocks of Si on the backside of Si pillar could be used as a protection to resist the high pressure in the molding process. However, simulation results show that mold voids location is dependent on the dicing line location. By fully etched method using silicon DRIE, large open areas could be achieved for mold filling purpose, the pillar geometry and supporting structures are optimized by the simulation results. Simulation results showed void free filling of the entire candidate molding compounds and without any supporting structures from additional layer. Therefore, the designs with the supporting structures to confirm the structural robustness of the pillars during the compression molding process 8' patterned Si wafer were molded. The results approved that no broken pillars perceived as well as voids free filling across the wafers. The method using partial dicing with mechanical supports was abandoned in the real test vehicles as it was proven to be unnecessary. Guided by the results of the molding simulations, test vehicles were fabricated and confirmed the newly proposed process platform for cost-effective MEMS wafer level packaging for capacitive sensors. Five materials from EMC (epoxy molding compound) to SMC (silicone molding compound) are evaluated in terms of voids and wire sweeping. The results show that SMC are inappropriate candidates. The EMC materials are evaluated by experiment and the results show no voids are perceived by CSAM (confocal scanning acoustic microscope).