Development of processor engine for FPGA based clock gating and performing power analysis

According to moors law scaling of technology with high performance and less power dissipation becoming hurdle in designing of processor engine. Power dissipation can be reduced by two ways by reducing static power dissipation and by reducing dynamic power dissipation. In this paper we are focusing on reduction in dynamic power dissipation of chip using latch free clock gating technique. We have applied our approach to 32bit Arithmetic and Logic unit with three different design styles like without clock gating, block enabled clock gating and function unit enabled respectively. These designs are simulated by Xilinx ISim simulator and Virtex-6 is used for synthesis and implementation and XPower analyzer helps to power analysis. We observed that our functional unit enable approach reduces power dissipation by an average of 65.35% and 52.24% for lower & higher frequencies respectively.