Efficient design and implementation of multiplierless FIR filter

FIR filter is a basic part used in Digital Signal Processing application because of its linear phase, stability, low cost and simple structure. The drawback of FIR digital filters is its high hardware complexity due to large number of multiplications. This paper introduced a novel design methodology for implementing Multiplierless FIR filter in hardware. The proposed algorithm aiming at the reduction of hardware cost by minimizing the number of sign power of two terms (non zero terms) in filter coefficient. In this paper, we implemented multiplierless FIR filter with and without optimized coefficients and their performances are compared in terms of speed, power, and area. It is observed that the power consumption for multiplierless FIR filter with unoptimized coefficient is 0.182W and the power consumption for multiplierless FIR filter with optimized coefficient is 0.176W. It also consumes fewer resources as compare to unoptimized coefficient multiplierless FIR filter.