FPGA based design and implementation of disparity estimation for stereo vision system

Stereo vision is an emerging technique requiring high quality depth computation in variety of applications in embedded and real-time systems. This system proposes implementation of cost computation information for stereo image pairs. High resolution disparity maps are needed to provide good image quality on auto stereoscopic displays that delivers stereo content without the need of 3-D glasses. Stereo matching is the key function of the stereo vision system. The purpose of stereo matching is to search for disparities between corresponding pixels in stereo images. This system implements FPGA architecture for cost estimation algorithm in stereo vision system; which is capable of processing images at real time. The stereo matching algorithm offers optimization for high depth quality. The SAD algorithm is implemented with window size of 5*5 for image resolution of 256*256. The proposed system is verified using Vitex-5 (ML 506) FPGA and Xilinx ISE Design Suite.