Algorithm for synthesis and exploration of clock spines

This work addresses the problem of developing a synthesis algorithm for clock spine networks, which is able to systematically explore the clock resources and clock variation tolerance. The idea is to transform the problem of allocating and placing clock spines on a plane into a slicing floorplan optimization problem, in which every candidate of clock spine network structures is uniquely expressed into a postfix notation to enable a fast cost computation in the slicing floorplan optimization. As a result, our synthesis algorithm can explore diverse structures of clock spine network to find globally optimal ones within acceptable run time. Through experiments with benchmark circuits, it is shown that our proposed algorithm is able to synthesize the clock spine networks with 38% reduced clock skew and 20% reduced clock skew variation over the clock tree structures, even 11% reduced clock power. Meanwhile, our clock spine networks have comparable tolerance to clock skew variation while using considerably less clock resources, reducing clock power by 36% over the clock mesh structures.