Power and speed efficient ripple counter design using 45 nm technology

A very high speed, power and area efficient asynchronous and synchronous up/down counter is required in many applications viz. digital memories, ADCs, DACs, microcontroller circuits, frequency dividers, frequency synthesizer etc. Lower area, high speed and low power consumption may met by reducing size of hardware. Hence as the applications are increasing, demand for smaller size and longer life batteries increases This paper derives area, power and speed efficient structure for 3-bit asynchronous up counter for VLSI designing as the size of chip is reducing day by day. As demonstrated in this paper that by using proposed flip flop for the designing of 3-bit asynchronous up counter, number of transistor count is reduced by 69.56%, power is reduced by 46.05% and speed is increased by 49.8% compare to conventional design.