Modeling linear VR for DDR4 termination scheme of ADDR/CMD/CTRL signals

A Gm-C topology based linear voltage regulator (VR) model to terminate address, command and control (ADDR/CMD/CTRL) signals was proposed in this work. A dynamic resistive divider (DRD) enabled accurate modeling of the load regulation curve and the transition from sink to source mode. Validation proved the model's accuracy to predict performance which in turn will enable optimization and avoid over-designing the power delivery network (PDN).