Effect of open faults in FPGA switch matrices on fault detection mechanisms

Field programmable Gate Arrays (FPGAs) are currently being used in the design and implementation of many modern systems. In this paper, the effect of open faults in FPGA switch matrices on the robustness of fault detection mechanisms is investigated. The error detection mechanism is studied in the context of the Duplication With Compare (DWC) technique. The programmable multiplexer with level restorer used inside the FPGA is studied for fail-safe design. An analysis for optimal level restorer transistor sizing has been derived. It is shown that the ratio between the size of the level restorer transistors and pass transistor of the programmable multiplexer should be around 5.5.