A 4.86 mW 15-bit 22.5 MS/s pipelined ADC with 74 dB SNDR in 90 nm CMOS using averaging correlated level shifting technique

This paper proposes an averaging correlated level shifting (Averaging-CLS) technique as a switched-capacitor amplification technique for reducing finite opamp gain error. The Averaging-CLS inverts the finite opamp gain error in the second amplifying phase and then averages it with that in the first amplifying phase. With Averaging-CLS, a high-resolution pipelined ADC can employ medium-accuracy high-efficiency ring amplifiers, which lowers the power consumption and cost of the ADC. Compared with conventional CLS, Averaging-CLS halves the sampling capacitance under the same SNR requirement. A 15-bit pipelined ADC, which operates from a 1.2 V power supply and utilizes an input range of 2.2 V peak-to-peak differential, was realized in a 90 nm CMOS technology. The ADC achieves a 74 dB peak SNDR at 22.5 MS/s conversion rate and consumes 4.86 mW, resulting in the Walden and Schreier Figure-of-Merits of 52.7fJ/conv.-step and 167.6dB, respectively.