Secure scan chain using test port for tester authentication

Design-for-Test (DFT) techniques have been developed to improve testability of integrated circuits. Among the known DFT techniques, scan-based testing is considered an efficient solution for digital circuits. However, scan architecture can be exploited to wage a side channel attack. Scan chains can be used to access a cryptographic core to extract the private encryption key. There is an emerging demand for a secure scan architecture while maintaining the testability. For a scan enabled chip, if an attacker is given unlimited access to apply all sorts of inputs to the Circuit-Under-Test (CUT) and observe the outputs the probability of success increases. In this paper, a solution is presented in which, initially the CUT requests the tester to provide a secret code for authentication. The tester authentication limits the access to the scan architecture to just known testers. Moreover, in the proposed solution the number of attempts to apply test vectors and observe the results through the scan architecture is limited to make brute-force attacks practically impossible.