VLSI-design and FPGA-implementation of GMSK-demodulator architecture using CORDIC engine for low-power application

This paper proposes low-power design of the Gaussian-Minimum Shift-Keying (GMSK) demodulator using baseband quadrature signals. High-level architecture of this demodulator incorporates CO-ordinate Rotation-DIgital Computer (CORDIC) engine to accept the in-phase and quadrature components from received GMSK signal to generate phase angle and magnitude of the GMSK signal vector at half the sampling frequency thereby reducing the power consumption. Additionally, the design of differentiator and synchronizer for the suggested GMSK demodulator has been carried out. The proposed demodulator is implemented in field-programmable gate-array (FPGA) and post-route simulated for functional verification. Thereafter, BER performance analysis of this design has been carried out in Additive White Gaussian Noise (AWGN) channel environment. Finally, the suggested architecture is synthesized and post-layout simulated using 90 nm CMOS technology node. It occupies a core area of 0.12 mm
²
with 17770 gates and consumes 4.42 mW at 167 MHz of clock frequency.